The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated circuit (ULSI) involves the use of metallic wiring that connects individual devices in a semiconductor chip to one another. The wiring interconnect network of the circuit includes two features: line features that traverse a distance across the chip, and via features which connect lines in different layers together. Historically, both layers are made from a dielectric material such as an inorganic glass like silicon dioxide (SiO2) or a fluorinated silica film deposited by plasma enhanced chemical vapor deposition (PECVD). This dielectric material insulates the conductive patterns that compose the metallic via and line structures, typically made of copper, tungsten, silver, gold or aluminum.
One method described in U.S. Pat. No. 7,579,137 of creating a wiring network on such small scale is known as the dual damascene (DD) process, shown schematically in FIGS. 1a-1g. In a standard DD process, an interlayer dielectric (ILD), shown as two layers, a via level dielectric 1-110 and a line level dielectric 1-120, are formed on a substrate 1-100, as shown in FIG. 1a. The two layers 1-110, 1-120 are shown separately for clarity of the process flow description. These two layers can be made from the same or from different insulating films, and in the former case can be applied as a single monolithic layer. A hard mask layer 1-130 is optionally employed to facilitate etch selectivity and can serve as a polish stop, as is well known in the art.
In the dual damascene process, the position of lines 1-150 and vias 1-170 can be defined lithographically in photoresist layers, 1-140, as shown in FIGS. 1b and 1d, and transferred into hard mask 1-130 and ILD layers 1-110, 1-120 using reactive ion etching processes. The process sequence shown in FIGS. 1a-1g is known as a “line-first” to approach because trenches 1-160 which house the line feature are etched first, as shown in FIG. 1c. Referring to FIG. 1d, after the trench formation, lithography is used to define a via pattern 1-170 in the photoresist layer 1-140 which is formed in the dielectric layers 1-110, 1-120 to generate a dielectric via opening 1-180.
A dual damascene via structure 1-190 and trench structure 191 is shown in FIG. 1e after the photoresist layer 1-140 has been stripped. The structures 1-190, 1-191 are coated with a conducting liner material or material stack 1-200 that will protect conductor metal lines and vias and serve as an adhesion layer between the conductor and the ILD (1-110, 1-120). The recesses are then filled with a conducting fill material 1-210 over the surface of the patterned substrate. The fill 1-210 can be accomplished by electroplating copper, although other methods such as chemical vapor deposition (CVD) and other materials such as Al or Au can also be used. The fill 1-210 and liner materials 1-200 are then chemically-mechanically polished (CMP) to be coplanar with the surface of the hard mask 1-130, as shown in FIG. 1f. 
A capping material or blanket film 1-220 is deposited over the metal 1-210, as is depicted in FIG. 1g, to passivate the exposed metal surface 1-210 and to serve as a diffusion barrier between the metal 1-210 and any additional ILD layers to be deposited over the film 1-220. Silicon nitride, silicon carbide, and silicon carbonitride films deposited by PECVD are typically used as the capping material 1-220. This process sequence is repeated for each level of interconnects on the device. Since two interconnect features are defined to form a conductor in-lay within an insulator by a single polish step, the process of FIGS. 1a-1g is designated a dual damascene process.
The above manufacturing methods for dual damascene structures typically to involve a minimum of two lithography exposures alternated with two reactive ion etch steps, as well as the deposition steps such as those shown in FIGS. 1a-1g. Typically two lithography steps are required. For each lithography step, there may be several reactive ion etch steps required to open any auxiliary layers such as antireflective coatings and hardmask stacks, as well as the dielectric material itself. In the is aforementioned BEOL lithography-etch-lithography-etch (LELE) process flow, inter-tool wafer exchange sequences for the processing of such layers directly impacts wafer throughput and adds to the cost of high-volume semiconductor nanofabrication. Therefore, there is a need to provide a method of forming a three dimensional lithographic pattern which can simplify the process flow, reduce production cost and increase throughput.